DocumentCode :
1133627
Title :
Double-least-significant-bits 2´s-complement number representation scheme with bitwise complementation and symmetric range
Author :
Parhami, B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California at Santa Barbara, Santa Barbara, CA
Volume :
2
Issue :
2
fYear :
2008
fDate :
4/1/2008 12:00:00 AM
Firstpage :
179
Lastpage :
186
Abstract :
A scheme is proposed for representing 2´s-complement binary numbers in which there are two least-significant bits (LSBs). Benefits of the extra LSB include making the number representation range symmetric (i.e. from -2k-1 to 2k-1 for k-bit integers), allowing sign change by simple bitwise logical inversion, facilitating multiprecision arithmetic and enabling the truncation of results in lieu of rounding. These advantages justify the added storage and interconnect costs stemming from the extra bit. Operation latencies show little or no change relative to conventional 2´s-complement arithmetic, thus making double-LSB representation attractive.
Keywords :
floating point arithmetic; 2´s-complement binary number representation; bitwise complementation; bitwise logical inversion; computer arithmetic; double-least-significant-bits; floating-point arithmetic; interconnect costs stemming; least-significant bits; multiprecision arithmetic; operation latencies;
fLanguage :
English
Journal_Title :
Circuits, Devices & Systems, IET
Publisher :
iet
ISSN :
1751-858X
Type :
jour
DOI :
10.1049/iet-cds:20070235
Filename :
4490220
Link To Document :
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