Title :
General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons
Author :
Lee, Bang W. ; Sheu, Bing J.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fDate :
9/1/1992 12:00:00 AM
Abstract :
Circuit cells for DRAM-style programmable synapses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution
Keywords :
CMOS integrated circuits; VLSI; neural nets; 0.2 s; CMOS VLSI circuits; DRAM-style; electrically programmable synapses; gain-adjustable neurons; hardware annealing; high packing density; neural chips; optimal solution searching; refresh cycle; Annealing; Circuit synthesis; Image processing; Large scale integration; Neural network hardware; Neural networks; Neurons; Threshold voltage; Transconductance; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
