DocumentCode :
1133698
Title :
Design methodology of Miller frequency compensation with current buffer/amplifier
Author :
Aloisi, W. ; Palumbo, G. ; Pennisi, S.
Author_Institution :
Dipt. di Ing. Elettr. Elettron. e dei Sist. (DIEES), Univ.´´ di Catania, Catania
Volume :
2
Issue :
2
fYear :
2008
fDate :
4/1/2008 12:00:00 AM
Firstpage :
227
Lastpage :
233
Abstract :
Current buffers/amplifiers are used in series to the Miller compensation capacitor with the aim of eliminating the positive zero introduced by the forward path. They are increasingly adopted because of their low-voltage features, high-speed performance and, recently, for their suitability to be used with large capacitive loads (when a current gain is introduced). The authors propose a novel and simple design approach for the frequency compensation of a two-stage amplifier exploiting a current buffer/amplifier. The procedure has been profitably applied to a class-AB two-stage CMOS operational transconductance amplifier, having a 100 pF load. In particular, three compensation networks were designed using a 1.3 pF, 0.6 pF and 250 fF compensation capacitor alternatively. Moreover, the adopted compensation topology provides an improvement in terms of power supply rejection ratio, which was also analytically demonstrated. Simulations that are in very good agreement with theoretical results are also given.
Keywords :
CMOS integrated circuits; buffer circuits; operational amplifiers; CMOS operational transconductance amplifier; Miller frequency compensation; current buffer;
fLanguage :
English
Journal_Title :
Circuits, Devices & Systems, IET
Publisher :
iet
ISSN :
1751-858X
Type :
jour
DOI :
10.1049/iet-cds:20060188
Filename :
4490226
Link To Document :
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