Title :
The Role of PLLs in Future Wireline Transmitters
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA
Abstract :
As data rates in wireline transmitters approach 80-100 Gb/s, phase-locked loops emerge as a serious bottleneck, requiring co-design of the clock and data paths. This paper describes speed, skew, and jitter issues at these rates and formulates the corruption due to effects such as the reference phase noise and the loop filter leakage. The phase noise performance of cascaded loops is also analyzed and a new transmitter architecture is proposed that substantially relaxes the speed and skew requirements.
Keywords :
millimetre wave filters; phase locked loops; phase noise; timing jitter; PLL; bit rate 80 Gbit/s to 100 Gbit/s; clock codesign; data path design; jitter effect; loop filter leakage; phase-locked loop; reference phase noise; wireline transmitter; Cascaded phase-locked loops (PLLs); dividers; frequency doublers; gate leakage; millimeter-wave circuits; multiplexers; oscillators; phase noise; random and deterministic jitter;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2009.2027507
