Title :
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters
Author :
Higuchi, Tatsuo ; Kameyama, Michitaka
Author_Institution :
Department of Electronic Engineering, Faculty of Engineering, Tohoku University
Abstract :
The ternary T-gate can be used as a basic building block to construct both combinational and sequential circuits. Since the T-gate is one kind of tree-type universal logic module, any combinational circuit can be built up with modular logic arrays. For constructing ternary memory elements, however, the T-gate is required to be static hazard-free. A theoretical study is done on the necessary conditions for the practical realization of the static-hazard-free T-gate. On the basis of the result obtained, the static-hazard-free T-gate is realized using the ECL technique. The static-hazard-free T-gates obtained here can be used as building blocks to construct memory elements. Various memory elements such as D flip-flap-flop (FFF), D master-slave FFF, B master-slave FFF, and counting FFF is constructed easily. Using these memory elements, three different types of ternary counters can be designed and realized. They are an asynchronous signed ternary counter, a synchronous signed ternary counter, and a counter based on a shift register. Their design methods are discussed. These ternary counters are superior to the binary ones in that the up-down cotnting can easily be carried out by one input signal.
Keywords :
Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting.; Combinational circuits; Counting circuits; Design methodology; Feedback; Field-flow fractionation; Logic arrays; Master-slave; Multivalued logic; Sequential circuits; Shift registers; Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1977.1674782