A High-Speed Threshold Gate Multiplier

A design for a multiplier is proposed which utilizes the extended switching properties of threshold elements. High-speed adders capable of adding more than two summands are constructed using minimal numbers of threshold gates. These are used to sum the partial products generated in the multiplication of two numbers. Several levels of these adders may be combined to reduce the number of summands to two without incurring any carry propagation delay. When the final addition is then performed to yield the product, the carry ripple delay is a minimum. The entire network uses fewer logic elements than in the iterative array approach and gives a significantly faster processing time.