• DocumentCode
    1134168
  • Title

    Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module

  • Author

    Kameyama, Michitaka ; Higuchi, Tatsuo

  • Author_Institution
    Department of Electronic Engineering, Faculty of Engineering, Tohoku University
  • Issue
    12
  • fYear
    1977
  • Firstpage
    1297
  • Lastpage
    1302
  • Abstract
    This correspondence presents a theoretical study on the synthesis of multiple-valued logic networks based on tree-type universal logic modules (T-ULM´s). The mathematical notation of T-ULM is introduced. On the basis of the mathematical properties, an algorithm for synthesizing an arbitrary logic function of n variables with a smaller number of modules is presented. In this algorithm, only true and constant inputs are allowed at input terminals. The algorithm consists of two parts. The first one is a functional decomposition, and the other one is the proper order of the expansion which is the problem of zinding the most incomplete tree structure. Thus it is established that the systematic and nonexhaustive procedure of the algorithm gives a suboptimal solution for the reduction of the number of T-ULM´s.
  • Keywords
    Compatible set, complex disjunctive decomposition, control variables, dependency, expansion, residue functions, row multiplicity, ternary T-gate, tree-type universal logic module (T-ULM), true and constant inputs.; Algebra; Control system synthesis; Integrated circuit technology; Logic circuits; Logic design; Logic functions; Minimization; Multivalued logic; Network synthesis; Tree data structures; Compatible set, complex disjunctive decomposition, control variables, dependency, expansion, residue functions, row multiplicity, ternary T-gate, tree-type universal logic module (T-ULM), true and constant inputs.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1977.1674797
  • Filename
    1674797