Reduction of Depth of Boolean Networks with a Fan-In Constraint

Author

Preparata, Franco P. ; Mulller ; Barak, Amnon B.

Author_Institution

Coordinated Science Laboratory and Department of Electrical Engineering, University of Illinois

Issue

5

fYear

1977

fDate

5/1/1977 12:00:00 AM

Firstpage

474

Lastpage

479

Abstract

In this paper we presentt family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates. We show that a Boolean expression with n literals and involving the connectivest AND and OR can be restructured so that the resulting network of AND and OR gates has depth at most Cllog2n + δ, where a < 0.415 and Clis 1.81, 1.38, 1.18, and 1 for maximum fan-in l of 2,3,4, and 5, respectively. If we additionally require that the amount of equipment of the resulting network be bounded by a linear function of n, it is possible to bound the depth by 2 log2n with a fan-in of at most 3.

Keywords

Boolean, expressions, combinational networks, computational complexity, design algrithms, fan-in, network depth, number of levels, parallel computation.; Arithmetic; Boolean functions; Computational complexity; Computer networks; Concurrent computing; Design methodology; Digital systems; Intelligent networks; Logic gates; Propagation delay; Boolean, expressions, combinational networks, computational complexity, design algrithms, fan-in, network depth, number of levels, parallel computation.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1977.1674864

Filename

1674864