• DocumentCode
    11350
  • Title

    Partitioned Model Order Reduction of Partial Element Equivalent Circuit Models

  • Author

    Romano, Daniela ; Antonini, Giulio

  • Author_Institution
    Dipt. di Ing. Ind. e dell´Inf. e di Econ., Univ. degli Studi dell´Aquila, L´Aquila, Italy
  • Volume
    4
  • Issue
    9
  • fYear
    2014
  • fDate
    Sept. 2014
  • Firstpage
    1503
  • Lastpage
    1514
  • Abstract
    As very large scale integration circuit speeds and density continue to increase, 3-D electromagnetic methods have become essential for the analysis, design, and verification of high-speed systems. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative to make them as compact as possible without compromising accuracy. To this aim, model-order reduction techniques can be successfully adopted. In this paper, we describe a partitioned Krylov subspace-based method for deriving reduced-order models directly from 3-D quasi-static partial element equivalent circuit models. The multiscale block decomposition method is adopted to speed-up the computation of the projection matrix; furthermore, the adaptive cross approximation and singular value decomposition techniques are used to achieve matrix compression exploiting the low-rank behavior of magnetic and electric field couplings. Results are presented on several examples to demonstrate the capabilities and speed of the proposed new method.
  • Keywords
    VLSI; approximation theory; equivalent circuits; high-speed integrated circuits; integrated circuit modelling; singular value decomposition; 3D electromagnetic methods; 3D quasistatic partial element equivalent circuit models; adaptive cross approximation; frequency domain computations; high-speed systems; low-rank behavior; magnetic-electric field couplings; matrix compression; multiscale block decomposition method; partitioned Krylov subspace-based method; partitioned model order reduction technique; projection matrix; reduced-order models; singular value decomposition techniques; standard circuit simulators; time domain computations; very large scale integration circuit; Complexity theory; Computational modeling; Integrated circuit modeling; Mathematical model; Matrix decomposition; Partitioning algorithms; Symmetric matrices; Acceleration techniques; adaptive cross approximation (ACA); generalized minimal residual; model order reduction (MOR); modified nodal analysis (MNA); partial element equivalent circuit (PEEC) method; singular value decomposition (SVD);
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2014.2338912
  • Filename
    6871333