DocumentCode
1135804
Title
Analytical modelling for the RESURF effect in JI and SOI power devices
Author
Popescu, A. ; Udrea, F. ; Ng, R. ; Milne, W.I.
Author_Institution
Dept. of Eng., Cambridge Univ., UK
Volume
149
Issue
56
fYear
2002
Firstpage
273
Lastpage
284
Abstract
The authors present a review and assessment of state-of-the-art analytical models which describe the breakdown behaviour of JI and SOI RESURF power devices. The results are compared with numerical values, and a short evaluation of strengths and weaknesses specific to each model is given. A new modelling concept for the breakdown regime in RESURF power structures is introduced, and the results are assessed against numerical values. The same technique can be used to derive the breakdown voltage of RESURF devices fabricated in JI and SOI technologies, and is potentially useful for non-standard technologies, such as linearly graded SOI, partial SOI and 3-D RESURF. The model provides accurate description for punch-through, non-punch-through and volume breakdown.
Keywords
power MOSFET; power field effect transistors; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; silicon-on-insulator; JI power devices; RESURF effect; SOI power devices; analytical modelling; breakdown behaviour; breakdown voltage; junction-isolated technology; linearly graded SOI; nonpunch-through effects; nonstandard technologies; punch-through effects; volume breakdown;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:20020517
Filename
1176567
Link To Document