• DocumentCode
    1135834
  • Title

    Accelerating Assertion Coverage With Adaptive Testbenches

  • Author

    Pal, Bhaskar ; Banerjee, Ansuman ; Sinha, Arnab ; Dasgupta, Pallab

  • Author_Institution
    Indian Inst. of Technol., Kharagpur
  • Volume
    27
  • Issue
    5
  • fYear
    2008
  • fDate
    5/1/2008 12:00:00 AM
  • Firstpage
    967
  • Lastpage
    972
  • Abstract
    We present a new approach to bias random test generation for accelerating assertion coverage. The novelty of the proposed approach is that it treats the design under test as a black box and attempts to steer the simulation toward coverage points that are relevant for targeted assertions purely through external control. We present this approach over three different models with varying degrees of observability and control. The results demonstrate a significant speedup in assertion coverage as compared to randomized simulation.
  • Keywords
    benchmark testing; integrated circuit design; integrated circuit testing; accelerating assertion coverage; adaptive testbenches; bias random test generation; black box; Automatic test pattern generation; Automatic testing; Circuit simulation; Computational modeling; Integrated circuit technology; Life estimation; Observability; Sequential analysis; Signal generators; Test pattern generators; Design verification; functional coverage; test generation;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.917975
  • Filename
    4492842