A 1-V–0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry

This brief presents a successive approximation register (SAR) analog-to-digital converter (ADC) that literally obviates the need for a reference supply. The reference (charge) of the digital-to-analog converter (DAC) is instead passively recovered from the residual input common-mode signal after each conversion. Such a fully passive DAC is proved to consume no switching energy in silicon, and the ADC is able to sustain a signal-to-noise-and-distortion ratio (SNDR) of 47 dB with only one supply even if the supply voltage varies from 1 to 0.6 V. Implemented in the 0.18- μm CMOS process, the ADC dissipates a linearly scalable dynamic power of 20.5-0.77 μW at a speed from 1.5 to 0.13 MS/s. As no power rail is connected to the DAC, the power supply modulation ratio is improved by 59 dB as compared to conventional designs. Without the need for a reference supply or a supply regulator, the ADC is able to share the same supply with digital systems while achieving energy-efficient data conversion regardless of the supply noise.