Reducing clock jitter by using Muller-C elements

A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element´s output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogue-to-digital conversion, and in clock distribution networks for VLSI systems.