Minimizing Latency in CCD Memories

Serial memories built from charge-coupled devices (CCD´s) offer an opportunity for minimizing latency times not available with the more conventional drum and disk (serial) memory units. Let r be the ratio of the maximum to the minimum clocking rates for the CCD memory. We show that in many practical situations the average latency can be reduced from 1/2 to 1/(1 + √r) of a revolution time if the optimal clocking strategy is used when the CCD is idle.