Logic synthesis speeds ASIC design

An explanation is given of logic synthesis, a design methodology whereby the designer begins by describing a design´s behavior in high-level code, and capturing its intended functionality rather than its implementation. Once the functionality has been thoroughly verified through simulation, the designer reformulates the design in terms of large structural blocks. The resulting description is called register-transfer level (RTL) since the equations describe how the data is transferred from one register to another. The designer simulates the RTL description and revises it as necessary to arrive at an acceptable high-level design. Logic synthesis provides two fundamental capabilities: automatic translation of high-level descriptions into logic designs, and optimization to decrease the circuit´s area and increase its speed. The capabilities and present limitations of the approach are examined.<>