Parasitic-aware RF circuit design and optimization

RF circuit synthesis techniques based on particle swarm optimization and adaptive simulated annealing with tunneling are described, and comparisons of parasitic-aware designs of an RF distributed amplifier and a nonlinear power amplifier are presented. Synthesized in 0.35-μm digital CMOS using a single 3.3-V power supply, the designs provide an 8-dB gain and 8-GHz bandwidth for a four-stage distributed amplifier, and 1.2-W output power with 55% drain efficiency at 900 MHz for a three-stage power amplifier. A standard circuit simulator, HSPICE or SPECTRE, embedded in an optimization loop is used to evaluate cost functions. The proposed design and optimization methodology is computationally efficient and robust in searching complex multidimensional design spaces.