DocumentCode
1137602
Title
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
Author
Reddy, Sudhaker M.
Author_Institution
Division of Information Engineering, University of Iowa
Issue
5
fYear
1978
fDate
5/1/1978 12:00:00 AM
Firstpage
455
Lastpage
459
Abstract
To improve the reliability of computer memories error-correcting and/or error-detecting codes have been successfully used. To provide for error control in systems organized to have b bits per card a new class of codes for simultaneous error correction and error detection is given.
Keywords
Binary codes; byte-error detecting codes; byte-per-card systems; linear codes; memories; Circuit faults; Computer errors; Decoding; Digital systems; Error correction; Error correction codes; Large scale integration; Linear code; Packaging; Parity check codes; Binary codes; byte-error detecting codes; byte-per-card systems; linear codes; memories;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1978.1675126
Filename
1675126
Link To Document