DocumentCode :
1137754
Title :
Efficiency of Random Compact Testing
Author :
Losq, Jacques
Issue :
6
fYear :
1978
fDate :
6/1/1978 12:00:00 AM
Firstpage :
516
Lastpage :
525
Abstract :
Random compact testing uses random inputs to test digital circuits. Fault detection can be achieved by comparing some statistic of the circuit under test, e.g., the frequency of logic ones at an output, with the value of that statistic previously determined for the fault-free circuit. In this paper, we show that random compact testing can efficiently detect failures in both combinational and sequential circuits. Although this testing method cannot guarantee detection of all faults, it provides a simple way to detect the vast majority of failures in most circuits. The effects of failures inside combinational circuits are modeled in relation to the statistical property measured by the test and a general evaluation of the testing efficiency is obtained. The probability of detection is shown to increase with the test length and to be dependent upon test parameters such as the statistics of the input sequence. For sequential circuits, the uncertainty of the initial state necessitates an initialization step, which is a long sequence of random inputs. The length of such an initialization sequence is circuit dependent, but for most circuits, proper initialization can be achieved in a few seconds. Most failures inside the memory elements are easily detected, even with short tests. Random compact testing can also detect most of the failures inside the excitation logic and the output circuitry. There, as for combinational circuits, its efficiency is largely dependent upon the test length. Some of the requirements and tradeoffs to achieve efficient detection are presented.
Keywords :
Combinational digital circuits; compact testing of digital circuits; random testing of digital circuits; sequential digital circuits; Circuit faults; Circuit testing; Combinational circuits; Digital circuits; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Sequential circuits; Statistical analysis; Combinational digital circuits; compact testing of digital circuits; random testing of digital circuits; sequential digital circuits;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1978.1675142
Filename :
1675142
Link To Document :
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