DocumentCode
1137835
Title
Efficient Algorithms for Testing Semiconductor Random-Access Memories
Author
Nair, Ravindra ; Thatte, Satish M. ; Abraham, Jacob A.
Author_Institution
Coordinated Science Laboratory, University of Illinois
Issue
6
fYear
1978
fDate
6/1/1978 12:00:00 AM
Firstpage
572
Lastpage
576
Abstract
A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in the fault model is described. The fault model is then extended to incorporate more complex faults. An 0(n · log2 n) algorithm is presented for one such extended fault model.
Keywords
Coupling; fault models; memories; test complexity; testing algorithm; Asynchronous circuits; Circuit faults; Electrical fault detection; Fault detection; Input variables; Inverters; Large scale integration; Logic circuits; Random access memory; Semiconductor device testing; Coupling; fault models; memories; test complexity; testing algorithm;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1978.1675150
Filename
1675150
Link To Document