• DocumentCode
    1138299
  • Title

    A Distributed Synchronized Clocking Method

  • Author

    Rolston, David R. ; Gross, David M. ; Roberts, Gordon W. ; Plant, David V.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Canada
  • Volume
    52
  • Issue
    8
  • fYear
    2005
  • Firstpage
    1597
  • Lastpage
    1607
  • Abstract
    This paper will present a novel method to generate and distribute a synchronous clock to multiple nodes in a distributed system. Total system synchronization is established by adjusting the internal delays of each node so that the delay between all adjacent pairs of nodes becomes identical. The system is based on the principles of phase-locked and delay-locked loops but does not discuss the methods and details of phase acquisition, jitter or lock-in time. The system is composed of a master node used to generate clock pulses and multiple slave nodes used to align the pulses. A Matlab Monte Carlo simulation of the linear behavior of the system is presented which not only validates the theoretical description, but also can be used as a good tool to gauge the performance of any particular system scenario. Selected HSpice simulations are then presented which show the operating characteristics of certain scenarios involving differing interconnect lengths between nodes that correspond to specific Matlab simulations.
  • Keywords
    Monte Carlo methods; circuit simulation; clocks; delay lock loops; distributed processing; phase locked loops; pulse circuits; synchronisation; Monte Carlo simulation; circuit simulation; clock pulse generation; delay-locked loops; distributed processing; distributed synchronized clocking method; distributed system; master nodes; phase-locked loops; pulse circuits; slave nodes; synchronization; synchronous clocks; Clocks; Delay; Frequency synchronization; Microprocessors; Phase locked loops; Pipelines; Pulse generation; Pulse measurements; Ring oscillators; Synchronous generators; Clock; distributed; phase-locked loop (PLL); synchronization;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2005.851683
  • Filename
    1495726