• DocumentCode
    1138632
  • Title

    A function-pipelined architecture and VLSI chip for MPEG video image coding

  • Author

    Wu, Chen-Mie ; Chou, Zi-Hong ; Chen, Yuan-Lin

  • Author_Institution
    Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan
  • Volume
    41
  • Issue
    4
  • fYear
    1995
  • fDate
    11/1/1995 12:00:00 AM
  • Firstpage
    1127
  • Lastpage
    1137
  • Abstract
    A function-pipelined architecture is presented for MPEG video image coding. Also, based on a 0.8 μm SPDM CMOS technology, a VLSI chip has been designed and implemented for such an architecture. The chip consists of 43,066 transistors and has a die size of 6,673 μm×5,260 μm (or 0.36 cm2). In the future, with such a VLSI chip, a coding processor will be developed for improving the performance of the MPEG video encoding system under development
  • Keywords
    CMOS digital integrated circuits; VLSI; digital signal processing chips; parallel architectures; pipeline processing; video coding; 0.8 μm SPDM CMOS technology; 0.8 micron; MPEG video image coding; VLSI chip; die size; function-pipelined architecture; performance; CMOS technology; Central Processing Unit; Consumer electronics; Discrete cosine transforms; IEEE news; Image coding; RLC circuits; Transform coding; Very large scale integration; Video compression;
  • fLanguage
    English
  • Journal_Title
    Consumer Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-3063
  • Type

    jour

  • DOI
    10.1109/30.477232
  • Filename
    477232
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1138632