An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits

Author

Rahman, H. ; Chakrabarti, C.

Author_Institution

Arizona State Univ., Tempe, AZ, USA

Volume

52

Issue

8

fYear

2005

Firstpage

496

Lastpage

500

Abstract

Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the subthreshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in $\\sim67\\hbox {\\%}$ leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.

Keywords

CMOS logic circuits; circuit simulation; leakage currents; logic design; logic gates; low-power electronics; CMOS logic circuits; ISCAS85 benchmark circuit; control point insertion technique; leakage current reduction; leakage power reduction; leakage reduction method; leakage sensitivity; low power design; minimum leakage vector; thin-oxide gate leakage; CMOS logic circuits; Circuit simulation; Degradation; Delay; Energy consumption; Gate leakage; Heuristic algorithms; Leakage current; Power generation; Subthreshold current; Control point insertion; leakage current reduction; leakage sensitivity (LS); low power design; minimum leakage vector (MLV);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2005.849026

Filename

1495757