Design and implementation of an efficient flash-based SSD architecture

Flash memory based solid-state disk (SSD) has shown a tremendous potential through its high performance. Recent studies mainly focus on the address mapping in the Flash Translation Layer (FTL) and improving the parallelism in the Flash Controller (FC). However, new features of NAND flash have allowed the performance loss caused by technical limitations to be fully offset by optimize the timing budgets throughout systems. In this paper, an FPGA-based high-performance SSD architecture is proposed to maximize the parallelism of commands and data in chip-level and bus-level. Performance evaluation based on the FPGA-based SSD architecture demonstrates that the bandwidth in hybrid pattern can be more than 65 percent better than the best of comparable SSD.