• DocumentCode
    1138978
  • Title

    Detection of Faults in Programmable Logic Arrays

  • Author

    Smith, James E.

  • Author_Institution
    Department of Electrical and Computer Engineering, University of Wisconsin
  • Issue
    11
  • fYear
    1979
  • Firstpage
    845
  • Lastpage
    853
  • Abstract
    A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.
  • Keywords
    Programmable logic arrays; fault detection; fault modeling; test generation; Circuit faults; Circuit testing; Fault detection; Logic arrays; Logic design; Logic programming; Logic testing; Manufacturing; Programmable logic arrays; System testing; Programmable logic arrays; fault detection; fault modeling; test generation;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1979.1675264
  • Filename
    1675264