DocumentCode
1139128
Title
Pipelined Hardware Structure for Sequency-Ordered Complex Hadamard Transform
Author
Bi, Guoan ; Aung, Aye ; Ng, Boon Poh
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
15
fYear
2008
fDate
6/30/1905 12:00:00 AM
Firstpage
401
Lastpage
404
Abstract
This letter presents a fast algorithm for the sequency-ordered complex Hadamard transform (SCHT) based on the decomposition method of decimation-in-sequency. To support high-speed real-time applications, a pipelined hardware structure is also proposed to deal with sequentially presented input/output data streams. This structure achieves a full hardware utilization and requires only complex adder/subtracters and complex data stores for an N-point SCHT.
Keywords
Hadamard transforms; mathematics computing; pipeline processing; complex adder; complex data store; complex subtracter; decomposition method; pipelined hardware structure; sequency-ordered complex Hadamard transform; Adders; Arithmetic; Bismuth; Digital signal processing; Hardware; Iterative algorithms; Matrix decomposition; Shift registers; Signal processing algorithms; Throughput; Fast algorithm; Hadamard transform; pipelined architecture;
fLanguage
English
Journal_Title
Signal Processing Letters, IEEE
Publisher
ieee
ISSN
1070-9908
Type
jour
DOI
10.1109/LSP.2008.922515
Filename
4494572
Link To Document