A new criterion for transient latchup analysis in bulk CMOS

A criterion for transient latchup of p-n-p-n structures initiated by current pulses is described. Based on the circuit-orient model, the terminal currents and voltages of the transistors as a function of the pulsed triggering currents are characterized, and the charge storage within p-n-p-n structures is investigated. It is found that, to maintain the regeneration process, the change of charge stored in junction depletion capacitances of a p-n-p-n structure must be greater than a certain value independent of the triggering currents. Thus, the criterion is constructed in terms of the constant charge storage within a p-n-p-n structure. Applying the criterion, latchup immunity against pulsed triggering currents can be evaluated with respect to process and device parameters. Both SPICE simulations and experimental results confirm the validity of the proposed transient criterion. It is found that the large transit time of bipolar transistors and large well-substrate junction depletion capacitance lead to higher latchup immunity against pulsed triggering currents