High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1×10¹⁸ cm^-3 together with a very shallow junction depth of less than 30 nm for the p⁺-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 μm. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p⁺-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate