DocumentCode :
1139388
Title :
Analysis of Limit Cycles in a Two-Transistor Saturable-Core Parallel Inverter
Author :
Lee, Fred C Y ; Wilson, Thomas G. ; Feng, Samuel Y M
Author_Institution :
Duke University Durham, N.C. 27706
Issue :
4
fYear :
1973
fDate :
7/1/1973 12:00:00 AM
Firstpage :
571
Lastpage :
584
Abstract :
A familiar two-transistor saturable-core parallel inverter is modeled as a nonlinear negative resistance in parallel with energy-storage elements. The techniques of singular-point analysis are combined with piecewise linear techniques to permit determination of solution trajectories on the phase plane. Clear insight is provided, not only into steady-state oscillation, but also into transient behavior of the circuit. Experimental results confirming the analytical model are included.
Keywords :
Circuit faults; Inductors; Inverters; Limit-cycles; Parasitic capacitance; Piecewise linear techniques; Semiconductor diodes; Steady-state; Switches; Switching circuits;
fLanguage :
English
Journal_Title :
Aerospace and Electronic Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9251
Type :
jour
DOI :
10.1109/TAES.1973.309641
Filename :
4103174
Link To Document :
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