Title :
System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip
Author :
Givargis, Tony ; Vahid, Frank ; Henkel, Jörg
Author_Institution :
Dept. of Inf. & Comput. Sci., Univ. of California, Irvine, CA, USA
Abstract :
In this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized system-on-chip (SOC) architecture to find all Pareto-optimal configurations. These Pareto-optimal configurations will represent the range of power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully applied our technique to explore Pareto-optimal configurations of our SOC architecture for a number of applications.
Keywords :
Pareto distribution; circuit layout CAD; circuit optimisation; directed graphs; embedded systems; integrated circuit layout; low-power electronics; system-on-chip; Pareto-optimal configurations; SOC architecture; directed graph model; embedded systems; low-power design; parameter dependencies; parameterized system-on-a-chip; platform-based design; power/performance design space; system-level exploration; Circuit optimization; Computer science; Embedded computing; Embedded system; National electric code; Power generation economics; Power system economics; Space exploration; System-on-a-chip;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.807764
