• DocumentCode
    1139492
  • Title

    Electrical Properties of Low- V_{T} Metal-Gated n-MOSFETs Using \\hbox {La}_{2}\\hbox {O}_{3}/\\hbox {SiO}_{x</h1></div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Author</span></div><div class='col-12 col-md-9 leftDirection leftAlign'><h2 class='mb-0 fw-semibold'>Chang, S.Z. ; Yu, H.Y. ; Adelmann, C. ; Delabie, A. ; Wang, X.P. ; Van Elshocht, S. ; Akheyar, A. ; Nyns, L. ; Swerts, J. ; Aoulaiche, M. ; Kerner, C. ; Absil, P. ; Hoffmann, T.Y. ; Biesemans, S.</h2></div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Author_Institution</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>Taiwan Semicond. Manuf. Co., Hsinchu</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Volume</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>29</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Issue</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>5</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fYear</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>2008</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fDate</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>5/1/2008 12:00:00 AM</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Firstpage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>430</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Lastpage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>433</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Abstract</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>In this letter, we report that by employing the La<sub>2</sub>O<sub>3</sub>/SiO<sub>x</sub> interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta<sub>2</sub>C metal-gated n-MOSFETs V<sub>T</sub> can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J<sub>G</sub> = 10 mA/cm<sup>2</sup> at 1.1 V), good drive performance (I<sub>on</sub> = 900 muA/mum at I<sub>soff</sub> = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>MOSFET; electric properties; hafnium compounds; high-k dielectric thin films; lanthanum compounds; semiconductor device reliability; silicon compounds; tantalum compounds; La<sub>2</sub>O<sub>3</sub>-SiO-HfLaO-Si-Ta<sub>2</sub>C; MOSFET; electrical properties; interfacial layer; positive-bias-temperature-instability reliability; ultrathin equivalent oxide thickness; CMOS technology; Crystallization; Degradation; Dielectric devices; Electrodes; Gate leakage; Hafnium compounds; MOSFET circuits; Microelectronics; Temperature distribution; <formula formulatype= $hbox{La}_{2}hbox{O}_{3}/ hbox{SiO}_{x}$ interfacial layer (IL); $hbox{Ta}_{2}hbox{C}$ ; HfLaO; low- $V_{T}$ n-MOSFETs;

  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2008.919780
  • Filename
    4494612
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1139492