مرکز منطقه ای اطلاع رساني علوم و فناوري - Electrical Properties of Low-<formula formulatype="inline"> <img src="/images/tex/665.gif" alt="V_{T}"> </formula> Metal-Gated n-MOSFETs Using <formula formulatype="inline"> <img src="/images/tex/755.gif" alt="\\hbox {La}_{2}\\hbox {O}_{3}/\\hbox {SiO}

Title :

Electrical Properties of Low- $V_{T}$ Metal-Gated n-MOSFETs Using $\\hbox {La}_{2}\\hbox {O}_{3}/\\hbox {SiO}_{x</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Author : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>Chang, S.Z. ; Yu, H.Y. ; Adelmann, C. ; Delabie, A. ; Wang, X.P. ; Van Elshocht, S. ; Akheyar, A. ; Nyns, L. ; Swerts, J. ; Aoulaiche, M. ; Kerner, C. ; Absil, P. ; Hoffmann, T.Y. ; Biesemans, S.</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Author_Institution : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>Taiwan Semicond. Manuf. Co., Hsinchu</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Volume : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>29</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Issue : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>5</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>fYear : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>2008</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>fDate : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>5/1/2008 12:00:00 AM</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Firstpage : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>430</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Lastpage : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>433</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Abstract : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>In this letter, we report that by employing the La<sub>2</sub>O<sub>3</sub>/SiO<sub>x</sub> interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta<sub>2</sub>C metal-gated n-MOSFETs V<sub>T</sub> can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J<sub>G</sub> = 10 mA/cm<sup>2</sup> at 1.1 V), good drive performance (I<sub>on</sub> = 900 muA/mum at I<sub>soff</sub> = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Keywords : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>MOSFET; electric properties; hafnium compounds; high-k dielectric thin films; lanthanum compounds; semiconductor device reliability; silicon compounds; tantalum compounds; La<sub>2</sub>O<sub>3</sub>-SiO-HfLaO-Si-Ta<sub>2</sub>C; MOSFET; electrical properties; interfacial layer; positive-bias-temperature-instability reliability; ultrathin equivalent oxide thickness; CMOS technology; Crystallization; Degradation; Dielectric devices; Electrodes; Gate leakage; Hafnium compounds; MOSFET circuits; Microelectronics; Temperature distribution; <formula formulatype=$ $hbox{La}_{2}hbox{O}_{3}/ hbox{SiO}_{x}$ interfacial layer (IL); $hbox{Ta}_{2}hbox{C}$ ; HfLaO; low- $V_{T}$ n-MOSFETs;