Title :
Simultaneous switching noise in on-chip CMOS power distribution networks
Author :
Tang, Kevin T. ; Friedman, Eby G.
Author_Institution :
Broadcom Corp., San Jose, CA, USA
Abstract :
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.
Keywords :
CMOS digital integrated circuits; ULSI; VLSI; equivalent circuits; inductance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; power supply circuits; switching transients; CMOS power distribution networks; SSN voltage; ULSI circuits; VLSI circuits; design constraints; inductive model; lumped RLC model; lumped inductive-resistive-capacitive model; on-chip inductance; on-chip power distribution networks; power supply rails characterization; simultaneous switching noise; synchronous CMOS circuit; transient current; ultra large scale integration; very large scale integration; CMOS logic circuits; Circuit noise; Network-on-a-chip; Power systems; RLC circuits; Semiconductor device modeling; Switching circuits; Ultra large scale integration; Very large scale integration; Voltage;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.800533
