Title :
A technique for Improving dual-output domino logic
Author :
Ramprasad, Sumant ; Hajj, Ibrahim N. ; Najm, Farid N.
Author_Institution :
Univ. of Illinois, Urbana, IL, USA
Abstract :
We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24%, respectively, over dual-output domino and a 48% power reduction for the largest circuit.
Keywords :
CMOS logic circuits; delays; logic design; logic gates; low-power electronics; timing; area reduction; clock load reduction; clock-generating domino; delayed clock; domino CMOS gates; dual-output domino logic; power reduction; CMOS logic circuits; Character generation; Circuit simulation; Clocks; Costs; Delay; Logic circuits; Logic gates; Power dissipation; Pulse inverters;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.800521
