Title :
Analysis of jitter in phase-locked loops
Author_Institution :
Mentor Graphics Corp., Allentown, PA, USA
fDate :
11/1/2002 12:00:00 AM
Abstract :
Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and long-term time-domain behavior of phase-locked loops. Particular attention is given to comparing the impact of 1/f noise and white noise in oscillators and frequency dividers on jitter in phase-locked loops of first- and second-order. Theoretical analysis is supported by results obtained using mixed-signal behavior simulation.
Keywords :
1/f noise; clocks; jitter; phase locked loops; time-domain analysis; white noise; 1/f noise; clock signal; free-running oscillator; frequency divider; jitter analysis; mixed-signal behavioral simulation; phase locked loop; time domain; white noise; Clocks; Frequency conversion; Jitter; Joining processes; Oscillators; Phase locked loops; Phase noise; Signal analysis; Time domain analysis; White noise;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
DOI :
10.1109/TCSII.2002.807265
