On the efficiency of parallel pipelined architectures

Author

Costa, Luciano Da Fontoura ; Slaets, Jan Frans Willem

Author_Institution

Dept. de Fisica e Ciencia dos Mater., Sao Paulo Univ., Brazil

Volume

39

Issue

9

fYear

1991

fDate

9/1/1991 12:00:00 AM

Firstpage

2086

Lastpage

2089

Abstract

A new approach is presented to the synthesis of efficient dedicated parallel pipelined architectures. The results can be used to determine the execution rates and the number of operators during the design of efficient parallel pipelined processors to be used, especially in digital signal processing and image processing. The conditions for maximum efficiency considering operators with different execution rates are verified in a simple and consistent way. Comments are also made on the practical application of these conditions and an application example is presented. The expressions presented can be used to produce a software oriented to the synthesis of efficient parallel pipelined architectures

Keywords

computerised signal processing; parallel architectures; pipeline processing; digital signal processing; efficient parallel pipelined processors; execution rates; image processing; parallel pipelined architectures; Algorithm design and analysis; Computer architecture; Digital signal processing; Fast Fourier transforms; Filtering; Hardware; Image processing; Pipelines; Signal mapping; Signal processing algorithms;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.134441

Filename

134441