A 250-MHz wave pipelined adder in 2-μm CMOS

Author

Liu, Wentai ; Gray, C. Thomas ; Fan, David ; Farlow, William J. ; Hughes, Thomas A. ; Cavin, Ralph K.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

29

Issue

9

fYear

1994

fDate

9/1/1994 12:00:00 AM

Firstpage

1117

Lastpage

1128

Abstract

Wave pipelining (also known as maximal rate pipelining) is a timing methodology used in digital systems to increase the number of effective pipelined stages without increasing the number of physical registers in the system. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic. Achieving a high degree of wave pipelining in CMOS technology requires careful study of delay balancing technique involving circuit design, layout method, and testing structure. A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-μm technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation

Keywords

CMOS integrated circuits; adders; digital arithmetic; integrated logic circuits; parallel processing; pipeline processing; 16 bit; 2 micron; 250 MHz; CMOS technology; MOSIS; combinational block; combinational logic; delay balancing technique; maximal rate pipelining; parallel adder; timing methodology; wave pipelined adder; Adders; CMOS logic circuits; CMOS technology; Circuit testing; Digital systems; Logic devices; Pipeline processing; Propagation delay; Registers; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.309908

Filename

309908