• DocumentCode
    1140639
  • Title

    Active devices under CMOS I/O pads

  • Author

    Chou, Kuo-Yu ; Chen, Ming-Jer ; Liu, Chi-Wen

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Taiwan, Taiwan
  • Volume
    49
  • Issue
    12
  • fYear
    2002
  • fDate
    12/1/2002 12:00:00 AM
  • Firstpage
    2279
  • Lastpage
    2287
  • Abstract
    Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (Vt2, It2) of ESD protection devices under various metal level stack structures, shows that i) It2 depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) Vt2 increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and DC electrical stress by transmission line pulse, as well as AC electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads are independent of bonding pad metal level structures.
  • Keywords
    CMOS integrated circuits; copper; electrostatic discharge; integrated circuit metallisation; integrated circuit modelling; protection; semiconductor device breakdown; system-on-chip; 130 nm; AC electrical stress; CMOS I/O pads; Cu; DC electrical stress; ESD protection devices; FSG low-k inter-metal dielectric; RC model; active devices; bonding mechanical stress; bonding pad metal level structures; capacitive-coupling experiments; dynamic impedance; eight-level Cu metal CMOS process; electrostatic discharge protection; fluorinated silicate glass dielectric; high current I-V curve; junction power dissipation criteria; metal level stack structures; ring-oscillator circuits; second breakdown trigger point; temperature cycling; thermal stress; Bonding; CMOS process; Circuit testing; Copper; Dielectric devices; Electrostatic discharge; Glass; Protection; Pulse measurements; Thermal stresses;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2002.807452
  • Filename
    1177995