Title :
Design of Totally Fault Locatable Combinational Networks
Author :
Goundan, Ayee ; Hayes, John P.
Author_Institution :
General Electric Company, Department of Ground Systems
Abstract :
The design of combinational logic networks is considered in which equivalent or indistinguishable stuck-type faults are confined to a small region of the network. A general type of fault equivalence called S-equivalence is introduced, which defines fault equivalence with respect to an arbitrary set of modules S. A network N is called totally fault locatable with respect to module set S, denoted TFLS, if all specified faults in N are S-equivalent. Some general structural properties of TFLS networks are derived. The problem of designing TFLS networks is investigated for S = {AND, OR, NAND, NOR, NOT} denoted AON, and S = {AON, EXCLUSIVE- OR} denoted AONE. All equivalent fault classes in TFLAON and TFLAONE networks can be identified by inspection. It is shown that every function has a TFLAONE network, that is, a realization where all equivalence classes can be identified by inspection, containing at most one control point or extra input. A method for constructing a TFLAONE realization of an arbitrary function is presented using at most one control point.
Keywords :
Combinational networks; easily testable networks; fault diagnosis; fault equivalence; logic design; totally fault locatable networks; Circuit faults; Circuit testing; Computer networks; Digital systems; Fault diagnosis; Fault location; Inspection; Logic circuits; Logic design; Logic testing; Combinational networks; easily testable networks; fault diagnosis; fault equivalence; logic design; totally fault locatable networks;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1980.1675454