Title :
A VLSI architecture for simplified arithmetic Fourier transform algorithm
Author :
Reed, Irving S. ; Shih, Ming-Tang ; Truong, T.K. ; Hendon, E. ; Tufts, D.W.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fDate :
5/1/1992 12:00:00 AM
Abstract :
The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed by I.S. Reed et al. (1990) for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25% of that used in the direct method
Keywords :
Fourier transforms; VLSI; digital arithmetic; digital signal processing chips; number theory; signal processing; AFT algorithm; Fourier analysis; VLSI architecture; butterfly structure; number-theoretic approach; signal processing; simplified arithmetic Fourier transform algorithm; Algorithm design and analysis; Arithmetic; Discrete Fourier transforms; Fast Fourier transforms; Fourier series; Fourier transforms; Helium; Performance analysis; Signal analysis; Very large scale integration;
Journal_Title :
Signal Processing, IEEE Transactions on
