High level performance model based design space exploration for energy-efficient designs on FPGAs

Energy efficiency has become a key performance metric in implementing application on FPGA. Several parameters such as parallelism, data layout, data re-usability etc. determine energy efficiency. Therefore a parameterized architecture is required to analyze the trade-offs and select the most energy-efficient design. However, increasing the number of parameters exponentially increases the number of possible designs in the design space. It then becomes infeasible to simulate all the designs as time consumed in each simulation is quite significant. In this paper, we perform a high-level performance model based design space exploration for 2D image convolution. This technique allows us to explore the design space quickly and efficiently. We first develop a high level performance model which would allow us to do a parameter sweep of the large design space quickly. The parameter sweep will provide us with a small number of promising designs which can be simulated to arrive at the most energy-efficient design. We prove that a small design subspace will contain the dominating designs with respect to the metric of Energy Efficiency. We simulate the designs from this subspace and show that there is a considerable overlap of 77% between the top designs identified by the performance model and the designs simulated from the dominating design subspace.