Analysis of surface state effect on gate lag phenomena in GaAs MESFET´s

Author

Lo, Shih-Hsien ; Lee, Chien-Ping

Author_Institution

Nat. Nano Device Lab., Hsinchu, Taiwan

Volume

41

Issue

9

fYear

1994

fDate

9/1/1994 12:00:00 AM

Firstpage

1504

Lastpage

1512

Abstract

A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET´s has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET´s are responsible for this slow transient phenomenon. The measured “hole-trap-like” DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N⁺-gate spacing and lower surface state densities are shown to have less gate lag effect

Keywords

Schottky gate field effect transistors; deep level transient spectroscopy; gallium arsenide; hole traps; semiconductor device models; surface electron states; GaAs; GaAs MESFETs; N⁺-gate spacing; charge exchange; gate lag phenomena; hole-trap-like DLTS signal; slow transient phenomenon; surface charge density; surface state effect; two-dimensional transient simulation; ungated access region; Dielectrics; Doping; Filling; Gallium arsenide; MESFETs; Passivation; Pulse inverters; Pulse measurements; Pulse modulation; Steady-state;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.310100

Filename

310100