Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
Abstract :
Low-power, compact, and high-performance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nanotube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET (CN-MOSFET) domino logic, and CN-MOSFET NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53%, 77.96%, and 15.52% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54%, 95.57%, and 25.66% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the other adder circuits that are evaluated in this study.
Keywords :
CMOS logic circuits; MOSFET circuits; adders; carbon nanotube field effect transistors; silicon; CN-MOSFET NP dynamic CMOS; CN-MOSFET domino logic; HSPICE simulation; NP dynamic CMOS circuits; Si; carbon nanotube MOSFET; carbon nanotube transistor technology; compact CMOS circuit; look-ahead adder; low power CMOS circuit; pipeline adder; propagation delay; silicon MOSFET domino logic; size 16 nm; Carbon based electronics; carbon nanotube transistor technology; domino logic; dynamic logic; electron mobility; high performance; hole mobility; low power;
