Title :
An ultra-high-speed ECL-BiCMOS technology with silicon fillet self-aligned contacts
Author :
Liu, Teyin M. ; Chin, Gen M. ; Jeon, Duk Y. ; Morris, Mark D. ; Archer, Vance D., III ; Johnson, Robert W. ; Tarsia, Maurice ; Kim, Helen H. ; Cerullo, Marcio ; Lee, Kwing F. ; Sung, Janmye James ; Lau, Kei-Shun ; Chiu, Tzu-Yin ; Voshchenkov, Alexander M.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
9/1/1994 12:00:00 AM
Abstract :
We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm2. A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology
Keywords :
BiCMOS integrated circuits; VLSI; digital integrated circuits; emitter-coupled logic; frequency dividers; integrated circuit technology; integrated logic circuits; metallisation; silicon; 0.5 micron; 0.6 micron; 13.5 GHz; 24 to 50 ps; 5 V; 8 Gbit/s; CMOS gate delay; ECL bipolar circuits; ECL gate delay; ECL-BiCMOS technology; SIFT process; Si; Si fillet self-aligned contacts; half-micron technology; single phase decision circuit; static frequency divider; super self-aligned technology; ultra-high-speed operation; BiCMOS integrated circuits; CMOS process; CMOS technology; Circuit optimization; Current density; Delay; Integrated circuit technology; Process design; Ring oscillators; Silicon;
Journal_Title :
Electron Devices, IEEE Transactions on
