Title :
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design
Author_Institution :
Dept. of Electron. Eng., Rome Univ., Italy
Abstract :
This paper provides a quantitative understanding of the relations among supply-voltage scaling, sustainable cycle time, pipeline depth, instruction-level parallelism, and power dissipation. Starting from simple well-established formulas, the analysis show that there is an optimal sizing of the target supply voltage and pipeline stage complexity to minimize power under a performance constraint. The verification of the model on five real processors is reported and discussed, and the application to an ideal microprocessor design or redesign is illustrated.
Keywords :
CMOS digital integrated circuits; VLSI; integrated circuit design; low-power electronics; microprocessor chips; pipeline processing; VLSI microprocessor design; instruction level parallelism; instruction-level parallelism; performance constraint; pipeline depth; power dissipation reduction; supply-voltage scaling; sustainable cycle time; system-level limits; CMOS technology; Capacitance; Clocks; Constraint theory; Delay; Microprocessors; Parallel processing; Power dissipation; Silicon on insulator technology; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.801549
