DocumentCode
1141790
Title
Testing Memories for Single-Cell Pattern-Sensitive Faults
Author
Hayes, John P.
Author_Institution
Departments of Electrical Engineering and Computer Science, University of Southern California
Issue
3
fYear
1980
fDate
3/1/1980 12:00:00 AM
Firstpage
249
Lastpage
254
Abstract
The design of minimum-length test sequences for pattern sensitivity in random-access memory (RAM) arrays is examined. The single pattern-sensitive fault (SPSF) model is used in which operations addressed to at most one memory cell are allowed to be faulty at any time. The influence of an SPSF affecting cell Ci is restricted to a fixed set of cells called the neighborhood of Ci. A new method is presented for efficiently generating the sequence of writes required in an SPSF test. This method yields optimal sequences for a useful class of neighborhoods called tiling neighborhoods. It is observed that RAM neighborhoods can be interpreted as polyominoes. A general procedure is given for constructing an SPSF test containing the minimum number of writes but a nonminimum number of reads. The difficult problem of minimizing the number of reads in an SPSF test is investigated for the 2-cell memory M2. A test of length 36 for M2 is derived which is optimal under certain reasonable restrictions. It is demonstrated that minimum-length SPSF tests can be inherently asymmetric.
Keywords
Fault detection; memory testing; pattern sensitivity; polyominoes; single pattern-sensitive faults; test generation; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Integrated circuit testing; Interference; Random access memory; Read-write memory; Test pattern generators; Fault detection; memory testing; pattern sensitivity; polyominoes; single pattern-sensitive faults; test generation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1980.1675556
Filename
1675556
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