DocumentCode :
1141800
Title :
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
Author :
Su, Stephen Y H ; Ducasse, Edgar
Author_Institution :
Department of Computer Science, School of Advanced Technology, State University of New York
Issue :
3
fYear :
1980
fDate :
3/1/1980 12:00:00 AM
Firstpage :
254
Lastpage :
258
Abstract :
This paper deals with a method for designing a digital system which will remain operational in spite of the failure of some of its components. A scheme and its realization are presented for automatically reconfiguring a 5MR (five modular redundancy system or 5-input majority voting system) into a triple modular redundancy (TMR) system under a single or double module failures. The scheme can tolerate a double fault followed by a single fault which can neither be tolerated by a 5MR nor by a hybrid redundancy system with a TMR core. It uses no spare units and the circuit realization is relatively simple. The modular structure of the logic design for the proposed scheme should make the testing of the system easier. The scheme can be used in both binary and multivalued systems.
Keywords :
Fault-tolerant computing; N-modular redundancy; fault-tolerant design; fault-tolerant systems; hybrid redundancy; multiple failures; multiple-valued logic; redundancy scheme; self- repair systems; system design; Circuit faults; Circuit testing; Design methodology; Digital systems; Hardware; Logic design; Logic testing; Redundancy; System testing; Voting; Fault-tolerant computing; N-modular redundancy; fault-tolerant design; fault-tolerant systems; hybrid redundancy; multiple failures; multiple-valued logic; redundancy scheme; self- repair systems; system design;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1980.1675557
Filename :
1675557
Link To Document :
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