Title :
Predicting system-level area and delay for pipelined and nonpipelined designs
Author :
Jain, Rajiv ; Parker, Alice C. ; Park, Nohbyung
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fDate :
8/1/1992 12:00:00 AM
Abstract :
The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time. A mathematical model for predicting the area-delay tradeoff curve for pipelined and nonpipelined data paths, given a data flow graph and a choice of module styles, is proposed. The model has been validated against designs generated by pipelined and nonpipelined data-path synthesis programs
Keywords :
circuit layout CAD; delays; logic CAD; pipeline processing; area-delay characteristics; data flow graph; delay prediction; module styles; nonpipelined data paths; pipelined designs; system-level area; Clocks; Delay systems; Design automation; Flow graphs; Mathematical model; Multiplexing; Parallel processing; Resource management; Space exploration; Wires;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
