Title :
Optimal floorplan area optimization
Author :
Wang, Ting-Chi ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fDate :
8/1/1992 12:00:00 AM
Abstract :
An optimal algorithm for the floorplan area optimization problem is presented. The algorithm is based on an extension of the technique of L. Stockmeyer (1983). Experimental results indicate that the authors´ algorithm is efficient and capable of successfully handling large floor plans. The algorithm is compared with the branch-and-bound optimal algorithm of S. Wimer et al. (ibid., vol.8, no.2, p.139-45, 1989). The running time of the present algorithm is substantially less than that of the Wimer algorithm. For several examples where the Wimer algorithm ran for days and did not terminate, the present algorithm produced optimal solutions in a few seconds
Keywords :
VLSI; circuit layout CAD; integrated circuit technology; optimisation; CAD; VLSI layout; floorplan area optimization; large floor plans; optimal algorithm; Circuit topology; Cost function; Design automation; Integrated circuit interconnections; Performance evaluation; Polynomials; Radio access networks; Very large scale integration; Wheels;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
