HALO: an efficient global placement strategy for standard cells

Author

Yang, Yeong-Yil ; Kyung, Chong-Min

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

Volume

11

Issue

8

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

1024

Lastpage

1031

Abstract

A standard cell placement procedure that is based on an efficient global placement strategy, called HALO (hierarchical alternating liner ordering), is proposed. This method generates a global 2D placement of circuit modules by hierarchical application of linear ordering in an alternating direction. The HALO global placement procedure is followed by a detailed placement procedure which consists of row assignment, feed-through cell assignment and intrarow cell assignment steps. Experimental results on two benchmark circuits, primary1 and primary2, consisting of 752 and 2907 cells, have shown decreases of the half-perimeter routing lengths by 7% and 24%, respectively, compared with the best available results obtained so far. Total CPU time, including the subsequent detailed placement, was less than half that of previously published work

Keywords

application specific integrated circuits; circuit layout CAD; computational complexity; integrated circuit technology; ASIC layout; HALO; circuit modules; feed-through cell assignment; global 2D placement; global placement strategy; intrarow cell assignment; linear ordering; row assignment; standard cells; Central Processing Unit; Circuits; Helium; Heuristic algorithms; Materials science and technology; Packaging; Partitioning algorithms; Routing; Space technology; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.149773

Filename

149773