DocumentCode
1142245
Title
Syndrome-Testable Design of Combinational Circuits
Author
Savir, Jacob
Author_Institution
IBM Thomas J. Watson Research Center
Issue
6
fYear
1980
fDate
6/1/1980 12:00:00 AM
Firstpage
442
Lastpage
451
Abstract
Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.
Keywords
Combinational circuit; fan-out-free circuit; minterm; prime implicant; single fault; stuck-at fault; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational efficiency; Costs; Design methodology; Electrical fault detection; Fault detection; Jacobian matrices; Combinational circuit; fan-out-free circuit; minterm; prime implicant; single fault; stuck-at fault;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1980.1675603
Filename
1675603
Link To Document