Title :
An automated electrical defect identification and location method for CMOS processes using a specially designed test chip
Author :
Comeau, Alain R. ; Laneuville, Jacques
Author_Institution :
MITEL Semicond., Bromont, Que., Canada
fDate :
8/1/1992 12:00:00 AM
Abstract :
A test chip (named Yieldchip) was designed, simulated, fabricated, and tested on a 3-μm process. The layout of the Yieldchip´s cells enables the test program to electrically locate and identify active faults, thereby automating the, classification of defects. The Yieldchip can detect more than one defect per circuit in most circumstances. The algorithm can identify the 21 simple defects of the cells and can be used as an expert system to extend this list. Unidentified detectable faults are flagged at all times and located if possible
Keywords :
CMOS integrated circuits; automatic testing; circuit analysis computing; expert systems; fault location; integrated circuit testing; 3 micron; CMOS processes; Yieldchip; algorithm; automated electrical defect identification; defect location; expert system; test chip; Automatic testing; CMOS process; Circuit faults; Circuit testing; Fault diagnosis; Inverters; Monitoring; Performance evaluation; Semiconductor device measurement; Semiconductor device modeling;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
